FPGA-Based Hybrid-Type Implementation of Quantized Neural Networks for Remote Sensing Applications

Recently, extensive convolutional neural network (CNN)-based methods have been used in remote sensing applications, such as object detection and classification, and have achieved significant improvements in performance.Furthermore, there are a lot of hardware implementation demands for remote sensing real-time processing applications.However, the operation and storage processes in floating-point models hinder the deployment of networks in hardware implements with limited resource and power budgets, Evolution of psychological distress with age and its determinants in later life: evidence from 17-wave social survey data in Japan such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).To solve this problem, this paper focuses on optimizing the hardware design of CNN with low bit-width integers by quantization.First, a symmetric quantization scheme-based hybrid-type inference method was proposed, which uses the low bit-width integer to replace floating-point precision.

Then, a training approach for the quantized network is introduced to reduce accuracy degradation.Finally, a processing engine (PE) with a low bit-width is proposed to optimize the hardware design of FPGA for remote sensing image classification.Besides, a fused-layer PE is also presented for state-of-the-art CNNs equipped with Batch-Normalization Analysis of Tidal Flood Management in the Coastal Region, West Aceh Regency and LeakyRelu.The experiments performed on the Moving and Stationary Target Acquisition and Recognition (MSTAR) dataset using a graphics processing unit (GPU) demonstrate that the accuracy of 8-bit quantized model drops by about 1%, which is an acceptable accuracy loss.The accuracy result tested on FPGA is consistent with that of GPU.

As for the resource consumptions of FPGA, the Look Up Table (LUT), Flip-flop (FF), Digital Signal Processor (DSP), and Block Random Access Memory (BRAM) are reduced by 46.21%, 43.84%, 45%, and 51%, respectively, compared with that of floating-point implementation.

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